This invention relates to a constant voltage circuit contained in a CMOS (complementary metal oxide semiconductor) integrated circuit, for generating a constant voltage to be used as a bias voltage for an oscillator, for example, and, more particularly, to a constant voltage circuit having an operation-stop function of the type in which a constant voltage output is controlled by an operation-stop control signal.
In the CMOS integrated circuit used in microcomputers, electronic wrist watches, etc., an oscillating circuit with a crystal resonator or a ceramic resonator is used to obtain an exact operating frequency. The oscillator using source common type inverter 1 as shown in FIG. 1 is a typical example of such an oscillator, and is disclosed in "Nikkei Electronics" 1982, June, Vol, 21, pp 215 to 216. In this oscillator, bias circuit 2 is made up of P-channel MOS transistors P4 and P5, N-channel MOS transistors N4 and N5, and current-restricting resistor R. Bias voltage V.sub.BIAS has a first-order dependency on power voltage V.sub.DD. This bias voltage is applied from bias circuit 2 to the gate of P-channel MOS transistor P1 of common source type inverter 1. With the application of this bias voltage, the current flowing into inverter 1 is made constant, and transistor P1 is used as a constant current source, which is not dependent on power voltage V.sub.DD. With such an arrangement, the oscillation-start voltage depends only on the threshold voltage V.sub.THN of N-channel MOS transistor N1. Therefore, if the amplification factor of inverter 1 is set at an appropriate value, the FIG. 1 circuit operates as an oscillator which is operable at low voltage, since the constant current circuit can operate at low current; hence, low power dissipation can be realized.
If such an oscillator, having low power dissipation and low current, and packed in an IC, is incorporated in a microcomputer, the power consumption of the oscillator is wasted when the microcomputer is in the power-down mode. The applicant of this patent application has proposed, in Japanese application No. 60-66775, an oscillator with an oscillation-stop function in which the oscillation is stopped by an oscillation-stop signal, as is shown in FIG. 2. Referring to FIG. 2, N-channel transistor N2 and P-channel transistor P2, which are switch-controlled by oscillation-stop control signal HOSC, are also incorporated in source common type inverter 1. Bias circuit 2 is also provided with P-channel transistor P3 which is switch-controlled by the control signal HOSC and N-channel transistor N3 which is switch-controlled by the output signal HOSC of CMOS inverter I1, which is used for inverting this HOSC signal.
P-channel transistor P3 and N-channel transistor N3 in bias circuit 2 are both in an off state when in a normal operating mode, i.e., when the HOSC signal is at logical level "1". Also, when in this mode, a predetermined bias voltage appears at output node Na. When in a hold mode (operation is stopped), i.e., when the HOSC signal is at logical level "0", P-channel transistor P3 and N-channel transistor N3 are both in an on state, and power voltage V.sub.DD appears at output node Na. In this mode, the P-channel transistor P1 of source common type inverter 1 is also in an off state. As a result, no current flows in inverter 1, thereby saving power.
In bias circuit 2, when the operation mode reverts from the hold mode to the normal mode, the bias voltage rises slowly, with the result that the oscillation-start time may be long, as is shown in FIG. 3. As can be seen in this figure, when in the hold mode, the output node Na is at V.sub.DD level. The instant the hold mode is ended, P-channel transistors P3, P4, and P5, and N-channel transistors N3, N4, and N5 are in the off state. Therefore, the output node Na is electrically in a floating state, and dynamically holds the V.sub.DD level. Depending on the amount of leakage current between the output node Na and the IC board, the potential at the output node Na gradually drops from the V.sub.DD level. In the course of the drop in potential, P-channel transistors P4 and P5 and N-channel transistors N4 and N5 are turned on. Thereafter, a fixed bias voltage appears at node Na, and the source common type inverter 1 initiates oscillation when the bias voltage output is V.sub.DD -(.vertline.V.sub.THP .vertline.+.alpha.). In this mathematical expression, V.sub.THP is the threshold voltage of the P-channel transistor P1 of the inverter 1, and .alpha. is an additional gate bias voltage for making the constant current flow in P-channel transistor P1.